1. Field of the Invention
The present invention relates generally to wireless communication systems, and more particularly, to a code division multiple access (CDMA) communication system having a circuit for providing compensation for phase errors due to clock jitter.
2. Background Art
Code Division Multiple Access (CDMA) is a form of digital cellular phone service that assigns a code to all speech bits, sends a scrambled transmission of the encoded speech over the air and reassembles the speech to its original format. CDMA combines each phone call with a code which only one cellular phone plucks from the air.
CDMA operates in conjunction with spread spectrum transmission. A transmitter takes the original information signal and combines it with a unique correlating code to produce a radio frequency (RF) signal that occupies a much greater bandwidth than the original signal. RF signals from several transmitters are spread across the same broad frequency spectrum. The dispersed signals are pulled out of the background noise by a receiver which knows the code. By assigning a unique correlating code to each transmitter, several simultaneous conversations can share the same frequency allocation.
A typical CDMA system comprises a plurality of cells or designated regions, a base station associated with each cell and a plurality of mobile units. CDMA systems require transmission schemes which efficiently use an allocated frequency band so that a maximum number of mobile units can be accommodated with a minimum amount of interference. In accordance with CDMA standards, a communication link from a mobile unit to a base station is called a reverse link, and a communication link from a base station to a mobile unit is called a forward link. Communication in the reverse link is particularly difficult because a base station must be able to distinguish among all of the information signals transmitted from mobile units located within its particular cell. To provide communication in the reverse link, a CDMA mobile unit has a transmitter that produces an RF carrier signal based on an information signal.
As shown in FIG. 1 of the drawings, a typical transmitter 20 of a CDMA mobile telephone set has a data input 21 for supplying a binary information sequence to be transmitted. For example, input data may be encoded using a Non-Return to Zero (NRZ) encoding scheme in -which ones and zeroes are represented by opposite and alternating high and low voltages. To utilize the entire available channel bandwidth, the phase of the carrier should be shifted pseudo-randomly according to pseudo-noise (PN) sequences. In CDMA cellular systems, pseudo-random data spreading is defined in the Telecommunication Industry Association (TIA)/Electronic Industry Association (EIA) Interim Standard TIA/EIA/IS-95-A (May 1995) entitled Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System, and incorporated herein as a reference.
To provide quadrature data spreading, input data is processed in in-phase (I) and quadrature-phase (Q) channels of the transmitter 20 using in-phase and quadrature-phased pilot pseudo-noise (PN) sequences PNI and PNQ, respectively, defined in the TIA/EIA/IS-95-A Standard. In accordance with this standard, the PNI and PNQ sequences are periodic signals generated at a rate of 1.2288 Mchip/sec based on characteristic polynomials.
Multipliers 22 and 24 are respectively arranged in I- and Q-channels to multiply the input data by PNI and PNQ sequences. Up-sampling circuits 26 and 28 up-sample output values of the multipliers 22 and 24, respectively, by a factor of 8. In addition, the Q-channel contains a delay circuit for delaying the output of the circuit 28 by xc2xd chip equal to 4 samples. The outputs of circuits 26 and 29 are supplied to n-tap finite impulse response (FIR) filters 30 and 32 respectively arranged in the I- and Q-channels. The up-sampling circuits 26 and 28, delay circuit 29 and the FIR filters 30 and 32 are defined in the TIA/EIA/IS-95-A standard for a factor 4 up-sampling.
Outputs of the FIR filters 30 and 32 are supplied to digital-to-analog (D/A) converters 34 and 36, respectively. For example, the outputs of the FIR filters 30 and 32 may be represented by 10-bit digital signals. The D/A converters 34 and 36 produce analog signals Vi and Vq respectively supplied via anti-aliasing low-pass filters (LPF) 38 and 40 to I and Q inputs of a transmitting circuit 42 that performs offset quadrature phase-shift keying (QPSK) to produce a modulated radio-frequency signal transmitted to a base station using an antenna 44.
To synchronize signal processing in the I- and Q-channels, the transmitter 20 comprises a digital synthesizer 46 that produces an internal clock signal in response to an external clock signal. The internal clock signal is supplied to the FIR filters 30 and 32 and to the D/A converters 34 and 36.
To support signal processing in the I- and Q-channels, the internal clock frequency of the transmitter 20 must be equal to a chip rate multiplied by 8. As the standard chip rate is equal to 1.2288 Mchip/sec, the internal clock must be produced at a frequency fx8 equal to 9.8304 MHz. However, to meet the frequency plan requirements of a CDMA mobile telephone, a reference clock supplied to the transmitter 20 may have a frequency fref different from 9.8304 MHz. For example, fref may be equal to 14.4 MHz.
In this case, fref/fx8=14.4 MHz/9.8304 MHz=375/156=1.468. Thus, in 375 cycles of the reference clock, 256 cycles of the internal clock are produced. Therefore, in order to produce an internal clock signal with 256 cycles, 119 clock cycles have to be removed from the 375 cycle reference clock.
The closest digital division ratio to 1.468 is 1.5. If this division ratio occurs over M cycles of the reference clock, then the number N of internal clock cycles removed over M cycles may be expressed as N=Mxe2x88x92(M/1.5)=119. Therefore, M=357. Accordingly, 357 out of 375 reference clock cycles are converted with the division ratio equal to 1.5, and for the remaining 18 cycles, the division ratio is equal to 1.
Thus, during the conversion of the reference clock into the internal clock, the division ratio must be changed, for example, from 1.5 to 1. As a result, jitter in the internal clock occurs.
For example, if the division ratio is changed from 1.5 to 1, the reference time t changes by a half cycle of the reference clock. The reference time change xcex94t is equal to xc2xd of {fraction (1/14.4)} MHz={fraction (1/28.8)} MHz=34.7 nanoseconds.
The clock jitter can be considered as parasitic xe2x80x9cramped phasexe2x80x9d modulation illustrated in FIG. 2. Such modulation causes substantial phase errors at the output of the transmitting circuit 42. For example, the parasitic phase step xcex94"THgr"pxe2x88x92p caused by the reference time change At can be expressed as follows:
xcex94"THgr"pxe2x88x92p=(xcex94t/Tx8)xc3x972xcfx80,
where Tx8 is the period of the internal clock.
Accordingly, xcex94"THgr"pxe2x88x92p=(9.8304/28.8)xc3x972 xcfx80=2.143 radian=34% of 1 cycle. In the above-illustrated example, the root-mean-square phase error xcex94"THgr"rms produced as a result of the clockjitter can be expressed as xcex94"THgr"rms=xcex94"THgr"/{square root over (12)}=0.6186 rad.
The phase error due to clock jitter causes an error voltage at outputs of the D/A converters. As a result, the transmitter 20 has a high level of spurious emissions radiated at frequencies outside the assigned CDMA channel. As shown in FIG. 3, which illustrates a simulated spectrum of a transmitted RF signal in a conventional CDMA reverse link, the transmitted RF signal has poor adjacent channel power ratio (ACPR), which characterizes spurious emissions outside the assigned CDMA channel. Spurious emissions and the method of their measurement are defined in the TIA/EIA/IS-98-A Interim Standard entitled Recommended Minimum Performance Standards for Dual-Mode Wideband Spread Spectrum Cellular Mobile Stations. The ACPR is the ratio of the adjacent channel power to the power of the in-channel signal. In accordance with the TIA/EIA/IS-98-A Interim Standard, the adjacent channel power for 30 kHz bandwidth is measured at the 900 kHz offset from the central frequency of the in-channel signal. In the example shown in FIG. 3, the in-channel signal power at the central frequency is about 43 dBm, and the adjacent channel power is about 14 dBm. Thus, the difference between these values representing the ACPR is equal to about 29 dB.
It would be desirable to provide compensation for phase errors caused by clock jitter, in order to improve the ACPR of a CDMA telephone set.
Accordingly, an advantage of the invention is in providing compensation for phase errors caused by clock jitter to improve the ACPR of a CDMA transceiver.
This and other advantages of the present invention are achieved at least in part by providing a spread spectrum communication device that comprises a data spreading circuit for spreading data by a PN sequence and filtering the spread data, a clock generation circuit for generating an internal clock signal based on a reference clock signal, and an interpolation circuit for performing interpolation of filtered spread data formed by the data spreading circuit to produce an adjusted spread data value that compensates for a phase error caused by jitter in the internal clock signal.
In accordance with a preferred embodiment of the invention, the interpolation circuit may comprise a shift register controlled by the internal clock signal to produce samples of the filtered spread data for sequential internal clock cycles. Further, the interpolation circuit may comprise a memory for storing compensation factors representing the internal clock jitter. The compensation factors may be pre-calculated for each internal clock cycle. An address generator controlled by the internal clock signal may provide the memory with an address signal indicating a memory location that stores a compensation factor for a current internal clock cycle.
Based on the samples of the filtered spread data and the compensation factors, the interpolator calculates the adjusted spread data value. For example, the interpolation circuit may perform a linear interpolation algorithm to determine the adjusted spread data value. In response to the adjusted spread data values, a digital-to-analog converter may produce voltage compensated for the clock jitter.
The clock generation circuit may convert cycles of the reference clock signal into the cycles of the internal clock signal using at least first and second division ratios. To reduce the clock jitter, the internal clock cycles produced using the second division ratio may be evenly distributed over the internal clock cycles produced using the first division ratio.
In accordance with one aspect of the invention, a system for compensating for phase errors caused by the clock jitter is provided in a CDMA reverse link. The compensating system comprises a sampling circuit responsive to digital data spread by a PN sequence and filtered by a filter for producing spread data samples for sequential internal clock cycles, a memory for storing compensation factors representing the internal clock jitter, and an interpolator that performs interpolation of spread data to determine adjusted spread data values that compensate for the phase errors caused by the clock jitter.
In accordance with a method of the present invention, the following steps are carried out to provide compensation for phase errors caused by jitter in the internal clock signal:
sampling digital data spread by a PN sequence and filtered by a filter to produce spread data samples for several sequential internal clock cycles, and
interpolating the spread data samples using compensation factors to determine an adjusted spread data value that compensates for the phase errors caused by the clock jitter.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.